Search - RAM vhdl

[Embeded-SCM Develop] DoubleDort_RAM

Description: 双口RAM控制时序仿真双口RAM控制时序仿真 -Control of dual-port RAM dual-port RAM timing simulation control timing simulation to control dual-port RAM Timing Simulation
Platform: | Size: 1350656 | Author: wangzhaohui | Hits:

[Embeded-SCM Develop] TESTRAM

Description: FPGA，双口RAM测试程序，仿真双口RAM工作时序，对时序的理解！适合对双口RAM不太了解的初学者使用！QUARTUSII8.0软件平台仿真通过！-FPGA, dual-port RAM testing procedures, simulation of dual-port RAM timing work, the understanding of the timing! Suitable for dual-port RAM of the beginners do not know much about the use of! Simulation software platform QUARTUSII8.0 through!
Platform: | Size: 447488 | Author: wangzhaohui | Hits:

[VHDL-FPGA-Verilog] TLC5510_IIPRAM1

Description: FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the test!
Platform: | Size: 3439616 | Author: wangzhaohui | Hits:

[VHDL-FPGA-Verilog] mem_ctrl_latest.tar

Description: 存储器控制FPGA程序，包括ram，fifo，sdram，flash等。-FPGA memory control processes, including ram, fifo, sdram, flash and so on.
Platform: | Size: 331776 | Author: zhangsan | Hits:

[Windows Develop] fifo_design

Description: 异步fifo的设计，能够很好的的完成，数据的缓冲，内部有ram存储器-The design of asynchronous fifo， Asynchronous fifo design, can be a good completion of the data buffer, internal ram memory
Platform: | Size: 2048 | Author: 孟霑 | Hits:

[Other] ram

Description: 代码实现了一个由32位寄存器组成的寄存器组，并有多个控制输入和两个输出，方便使用。-The code implements a 32-bit register consisting of registers, and there are multiple control inputs and two outputs, easy to use.
Platform: | Size: 10240 | Author: Pang scotto | Hits:

[VHDL-FPGA-Verilog] components

Description: quartus的几个IP核（PWM,RAM,I2C）-quartus several IP core (PWM, RAM, I2C)
Platform: | Size: 226304 | Author: 宋瑞 | Hits:

[Embeded-SCM Develop] DW8051

Description: 8051Ip核内部ram。很多8051iP核都没有内部ram，上传一个希望对大家有用-internel ram of 8051Ip
Platform: | Size: 73728 | Author: 刘超 | Hits:

[VHDL-FPGA-Verilog] RAM.ZIP

Description: VHDL CODE FOR RAM AND ROM
Platform: | Size: 1024 | Author: praba | Hits:

[VHDL-FPGA-Verilog] BS

Description: 用EDA设计ROM和RAM及其应用，用VHDL语言编程实现字符、汉字的存取并用点阵显示-ROM and RAM design with the EDA and its applications, using VHDL programming language characters, Chinese characters, access to and use dot-matrix display
Platform: | Size: 13039616 | Author: 黄奇家 | Hits:

[Other] jj

Description: 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采样和数据存储回放。经测试，系统整体指标良好，垂直灵敏度和扫描速度等各项指标均达到设计要求。-The problem to design a digital storage oscilloscope, to Xilinx, 200,000 FPGA chip as the core, supplemented by the necessary peripherals (including signal conditioning, sample and hold, internal trigger, A/D converter, D/A conversion and I/O modules) the use of VHDL language programming, arbitrary waveform one-shot, continuous playback is triggered, and storage, in accordance with the requirements of the vertical sensitivity and sweep speed of the gear set. Signal acquisition, it will be the external input signal conditioning by the signal conditioning modules to the A/D circuit input range, after A/D converted into the FPGA s internal dual-port RAM for high-speed cache, and the results through the D/A converter to give general oscilloscope shows completed, the low-frequency signals in real-time sampling and high-frequency signals equivalent sampling and data storage playback. Been tested, the system as a whole indices are good, the vertical sensitivity and scan speed indicators meet
Platform: | Size: 546816 | Author: 黄奇家 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 设计了一个具有双时钟信号，双复位信号的FIFO，用于FPGA中的数据缓冲，RAM的定义是参数型，可以根据自己的需求，修改此参数，完成RAM的容量扩展。程序中有详细的说明-Designed a dual-clock signal, double reset signal FIFO, for the FPGA in the data buffer, RAM is defined as parameter type, according to their needs, and modify this parameter, the completion of the capacity expansion of RAM. Procedures described in detail
Platform: | Size: 183296 | Author: luosheng | Hits:

[VHDL-FPGA-Verilog] ahb_ram

Description: AHB接口的ram控制器，可靠性非常强。除了两个周期内发生读到写或写到读的极限情况（一般处理器设计中不会有这种传输方式），其他传输方式完全没有问题-AHB interface ram controller, reliability is very strong. In addition to occurring in two cycles read or write read write the limit (usually processor design will not have such means of transmission), other means of transmission is no problem
Platform: | Size: 1024 | Author: Jasking Wu | Hits:

[VHDL-FPGA-Verilog] VHDLcodes

Description: Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.
Platform: | Size: 6144 | Author: Vijay | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 包含CPU每部分器件的编写，通过改写RAM内容，可实现CPU简单运算的仿真-Some devices include the preparation of each CPU, RAM by rewriting the content, enabling easy operation simulation CPU
Platform: | Size: 2151424 | Author: Sophie | Hits:

[VHDL-FPGA-Verilog] VGA

Description: 压缩包中包含了用Verilog编写的视频控制模块，实现PAL制式到VGA制式的实时转换，同时包含了VGA专用ram配置模块，可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram configuration module can be directly useful
Platform: | Size: 79872 | Author: 熊文 | Hits:

[VHDL-FPGA-Verilog] RamFifoVHDL

Description: Ram Fifo Core VHDL file
Platform: | Size: 21504 | Author: Marcos Vinícius | Hits:

[VHDL-FPGA-Verilog] ram

Description: 用VHDL描述了RAM的读写,很好的一个小东东,要你好好学习,用于开发RAM-OK,OK,VHDL ,FPGA,RAM,WRITE AND READ ,YOU WILL LIKE IT,ARE YOU?
Platform: | Size: 168960 | Author: greetree | Hits:

[VHDL-FPGA-Verilog] BoXingFaSheng

Description: 多功能波形发生器VHDL程序与仿真功能：实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波 --A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成 --各种波形的线形叠加输出。 --说明： SSS（前三位）和SW信号控制4种常见波形种哪种波形输出。4种波形的频率、 --幅度(基准幅度A)的调节均是通过up、down、set按键和4个BCD码置入器以及一 --个置入档位控制信号（ss）完成的（AMP的调节范围是0~5V，调节量阶为1/51V）。 --其中方波的幅度还可通过u0、d0调节输出数据的归一化幅值（AMP0）进行进一步 --细调（调节量阶为1/（51*255）V）。方波A的占空比通过zu、zp按键调节（调节 --量阶1/64*T）。系统采用内部存储器——RAM实现任意输入波形的存储，程序只支 --持键盘式波形特征参数置入存储，posting 为进入任意波置入(set)、清除（clr）状态 --控制信号，SSS控制存储波形的输出。P180为预留端口 -Wave Generator
Platform: | Size: 10240 | Author: 梁辰 | Hits:

[VHDL-FPGA-Verilog] ram

Description: vhdl program for random access memory and sequence detector
Platform: | Size: 1024 | Author: swap | Hits:

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[Embeded-SCM Develop] DoubleDort_RAM

[Embeded-SCM Develop] TESTRAM

[VHDL-FPGA-Verilog] TLC5510_IIPRAM1

[VHDL-FPGA-Verilog] mem_ctrl_latest.tar

[Windows Develop] fifo_design

[Other] ram

[VHDL-FPGA-Verilog] components

[Embeded-SCM Develop] DW8051

[VHDL-FPGA-Verilog] RAM.ZIP

[VHDL-FPGA-Verilog] BS

[Other] jj

[VHDL-FPGA-Verilog] FIFO

[VHDL-FPGA-Verilog] ahb_ram

[VHDL-FPGA-Verilog] VHDLcodes

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] VGA

[VHDL-FPGA-Verilog] RamFifoVHDL

[VHDL-FPGA-Verilog] ram

[VHDL-FPGA-Verilog] BoXingFaSheng

[VHDL-FPGA-Verilog] ram

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